Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh, et. al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
A dielectric metal oxide material can be employed for a blocking dielectric layer that provides electrical isolation between control gate electrodes and memory elements configured to store electrical charges. In case the dielectric metal oxide blocking dielectric layer is formed inside a memory opening, a bottom portion of the dielectric metal oxide blocking dielectric layer needs to be removed by an anisotropic etch to physically expose a semiconductor surface of the substrate prior to forming a vertical semiconductor channel. However, anisotropic etch of the dielectric metal oxide material of the blocking dielectric layer poses a challenge due to low selectivity of the etch process and relative high collateral etch rate of the vertical portions of the blocking dielectric layer.